Mary Sajin Sanju.I

M. Vadivel


The arithmetic logic unit (ALU) is an important building block in many applications such as microprocessors, digital signal processors (DSPs) and image processing. Power efficiency may be a general concern in VLSI design. This paper presents delay-time optimization of a 4-bit ALU designed using the full-swing gate diffusion input (GDI) technique. An efficient ALU was designed and simulated by using HSPICE tool using 130nm technology. The modified ALU gives better performance in terms of power, delay and energy and can be used for high-speed and low-power applications.